(1) Field of the Invention
The present invention relates to a clock generator circuit for generating a plurality of clock signals with different phases, a signal multiplexing circuit (multiplexer circuit) including the clock generator circuit, and an optical transmitter including same, preferably in an optical communication system, and a clock generation method.
(2) Description of Related Art
In recent years, in the field of an optical communication system, for example, an optical transmitter etc. thereof, there is a need for a multiplexer circuit capable of operating at high speed at high frequency with sufficient reliability.
In the conventional multiplexer circuit, for example, when there are to be multiplexed 4-channel input data signals based on clock signals, two multiplexed data signals are generated first by multiplexing the input data signals on a 2-channel basis or per two channels. Thereafter, these multiplexed data signals are multiplexed further, whereby there is generated a multiplexed data signal in which 4-channel data signals are multiplexed.
In this case, since frequency-divided clock signals with the same phase are to be used in multiplexing on a 2-channel basis or per two channels, there are produced the same phase relationship between two multiplexed data signals generated by multiplexing on a 2-channel basis. In further multiplexing such multiplexed data signals with the same phase, when the multiplexed data signals with the same phase are selected based on clock signals with aligned edge timing (in the event of lack in phase margin between the two multiplexed data signals and the clock signals), a slight displacement in the clock signal timing (phase) will result in failure to multiplex the signals. Therefore, in order to obtain optimal phase timing, a latch circuit (for example, a D latch) is provided so as to produce a phase difference, by providing a phase shift of π of the two multiplexed data signals intended to be selected relative to each other, thereby achieving a timing margin (phase margin). With this provision, highly reliable signal multiplexing processing can be carried out even when high-speed operation at high frequency is required.
However, the above-configured multiplexer circuit needs the latch circuit (for example, D latch) and a circuit for supplying a clock thereto, and the like, which results in problematically an increase in circuit size and the power consumption, as well as preventing high-speed operation.
Accordingly, the inventor of the present invention has proposed a multiplexer circuit for multiplexing data signals, by use of a toggle flip-flop (TFF) which outputs, as clock signal, two frequency-divided clock signals with a phase difference of π/2 relative to each other, so as to prevent the increased in circuit size while achieving optimal phase timing (data timing), and to reduce the power consumption. (For example, refer to the Japanese Patent Laid-Open (Kokai) 2004-147075.)
Here, as an example of π/2 phase-difference signal generator circuit having a toggle flip-flop (TFF), there is the one disclosed in Japanese Patent Laid-Open (Kokai) Hei-5-037315.